Modern electronic devices, such as computers, often include complex circuitry embodied on a substrate. In many configurations, the substrate is a printed circuit board (PCB), which can include a plurality of layers stacked vertically, with each layer configured for a particular function, such as, for example, signal wiring, power, or ground (GND). The particular arrangement of layers is a function of both the operational requirements of the circuit and the design and other constraints imposed by the design engineers.
One such design constraint is the number and placement of electromagnetic compatibility (EMC) capacitors in a circuit and/or card. EMC effects have become a major concern as clock speeds increase to ever higher rates. EMC capacitors decrease unwanted radiation produced by the systems in which they are employed, such as, for example, computers, servers, and test equipment. Additionally, current domestic rules and regulations require one EMC capacitor for every square inch of a voltage power shape in any layer of a printed circuit board.
As such, engineering design objectives and regulatory requirements together result in an increasing number of EMC capacitors employed on any particular circuit board. Increased EMC capacitors drives up the total cost of capacitors on the systems. Moreover, EMC capacitors couple to circuit boards through coupling holes bored through the substrate. These coupling holes decrease already scarce board space and greatly complicate wiring layout on the board.
Typical methods and systems configured to solve the congested wiring problem add additional circuit board layers to provide more room for signal wiring. This approach, however, typically increases the printed circuit board cost and increases the design time and complexity.
Therefore, there is a need for a system and/or method for power domain design that addresses at least some of the problems and disadvantages associated with conventional systems and methods.